This invention relates generally to a multi-chip RF power amplifier, and more particularly the invention relates to packaging a multi-chip RF power amplifier.
Semiconductor power amplifiers typically comprise a plurality of semiconductor chips with each chip embodying a transistor amplifier, such as a silicon laterally diffused MOS field effect transistor (LDMOSFET). The transistor amplifiers can be operated in parallel to provide an increased power amplifier output, or the transistor amplifiers can comprise a main or carrier amplifier for maximum back-off power operation and a plurality of auxiliary or peak amplifiers which are suitably biased to begin operation sequentially for increasing power requirements. Such a power amplifier is described in copending application Ser. No. 10/059,866, supra.
Conventional practice is to individually package each transistor amplifier in a housing, and then connect the packaged transistor amplifiers through impedance matching networks and signal splitters to a common input. However, the use of individual chip packages increases manufacturing costs and increases the total package footprint on a supporting substrate. Further, the mounting of several packages necessarily increases transistor spacing and signal phase differences between the transistors.
In accordance with the invention, a plurality of individual transistor amplifier chips are mounted within a single package with each chip having its own input and output leads. The chips can have unequal peripheries and gate widths, as often employed in a Doherty amplifier, and each chip can be pre-matched within the package for its input, output, and bias leads. The prematched transistor dice can then be used in high-efficiency amplifier designs, such as for carrier and peak amplifiers in a Doherty configuration.
The invention provides manufacturing efficiency and reduces the overall packaging footprint. Further, the transistor dice are in close proximity thereby minimizing phase differences in signals in the several transistors. For a Doherty application, the package must have twice the number of leads as there are chips in the package. This allows each transistor to be individually pre-matched within the package and individually biased.
The invention and objects and features thereof would be more readily apparent from the following detailed description and dependent claims when taken with the drawings.